By Elie Maricau
This ebook specializes in modeling, simulation and research of analog circuit getting older. First, all vital nanometer CMOS actual results leading to circuit unreliability are reviewed. Then, transistor getting older compact versions for circuit simulation are mentioned and several other equipment for effective circuit reliability simulation are defined and in comparison. finally, the influence of transistor getting older on analog circuits is studied. Aging-resilient and aging-immune circuits are pointed out and the effect of expertise scaling is mentioned.
The versions and simulation options defined within the publication are meant as an reduction for gadget engineers, circuit designers and the EDA neighborhood to appreciate and to mitigate the effect of getting older results on nanometer CMOS ICs.
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Additional resources for Analog IC Reliability in Nanometer CMOS
If the source circuit generates noise in the conductor, in the form of alternating current, the voltage over the finite-impedance conductor is modulated. Therefore, the current going to the victim circuit is also modulated and the operation of the victim circuit might be affected. Electric field coupling, on the other hand, results from capacitive coupling between different interconnect nets. In the same way, magnetic coupling can be modeled by coupled inductors (Redoute 2009). 2. Simultaneous switching noise (SSN) is a particular case of common impedance crosstalk when subcircuits on the same IC share the same power distribution bus.
Two major sources of process variability are distinguished: local or intradie and global or interdie effects. Local variability results in parametric variations of identically designed transistors across a short distance, typically within the same circuit. This is also referred to as device mismatch. Global variability refers to variations between devices that are separated by a long distance or that are fabricated at a different time. Typically global variability is variability from die to die, wafer to wafer or lot to lot.
HKMG devices allow larger physical oxide thicknesses, but still suffer from large oxide thickness variations due to the roughness of the interface between the silicon and the high-k layer and between the high-k layer and the metal gate (saha 2010). High-k gate dielectrics also suffer from fixed charges in the gate-oxide layer. These charges can affect the carrier mobility and the VTH . As a consequence, variations in the location of these charges may affect the distribution of the mobility and the VTH (Kaushik et al.